1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a contact pad.
2. Description of Related Art
Currently, the aspect ratio of a node contact hole and a contact hole is increased as the integration of the integrated circuit is increased, so that it is difficult to open the node contact hole and the contact hole in a photolithography and etching process. Hence, a contact pad formed on a source/drain region is used as a contact medium between the source/drain region and a node contact (or a contact) to overcome the problem of opening the node contact hole or the contact hole.
FIGS. 1A through 1D are schematic, cross-sectional views of the conventional process for manufacturing a node contact hole.
As shown in FIG. 1A, a substrate 100 having a shallow trench isolation (STI) 102, a source/drain region 104, a gate structure 106 and an inter-layer dielectric (ILD) layer 108 is provided. The STI 102 is formed in the substrate 100. The gate structure 106 is formed on the substrate 100 and the source/drain regions 104 are formed in the substrate 100 exposed by the gate structure 106. The ILD layer 108 is formed over the substrate 100. An opening 110 is formed in the ILD layer 108 and exposes a portion of the source/drain region 104. A polysilicon layer 112 is formed over the substrate 100 and fills the opening 110.
As shown in FIG. 1B, a portion of the polysilicon layer 112 is removed by chemical-mechanical polishing (CMP) or etching back to expose the surface of the ILD layer 108. The remaining polysilicon layer 112 forms a contact pad 112a. An interpoly dielectric layer (IPD) 114 is formed over the substrate 100.
As shown in FIG. 1C, a bit-line opening 116 is formed to penetrate through the IPD layer 114 and the ILD layer 108 and exposes a portion of the source/drain region 104. A polysilicon layer (not shown) is formed over the substrate 100 and fills the bit-line opening 116. The polysilicon layer is patterned to form a bit line 116a in the bit-line opening 116.
As shown in FIG. 1D, a dielectric layer 118 is formed over the substrate 100. A node contact hole 120 aligned with the contact pad 112a is formed to penetrate through the dielectric layer 118 and the IPD layer 114 and exposes the contact pad 112a.
While the node contact hole is formed, misalignment may occur, as shown in FIG. 2. In FIG. 2, an opening formed when misalignment occurs is denoted by 222, while the reference numbers of the other components are the same as that in FIG. 1D since the manufacturing procedure of those components are the same as that illustrated by FIG. 1D. Because the opening 222 merely exposes a portion of the contact pad 112, the contact area between the contact pad 112 and the subsequently formed node contact is relatively small. Hence, the contact resistance between the contact pad 112 and the subsequently formed node contact is increased. Additionally, the materials of the dielectric layer 118, the IPD layer 114 and ILD layer 108 are similar to each other, so the etching depth cannot be easily controlled and the opening 222 easily penetrates through the IPD layer 114 and into the ILD 108 to form a trench 222a adjacent to the contact pad 112a. Moreover, in the subsequent formation of the node contact in the node contact hole, it is difficult to fill the trench 222a with polysilicon material, so that a void is formed in the trench 222a. These conditions lead to electrical failure of the device. Typically, in order to overcome the problem caused by the misalignment of the node contact hole, the size of the node contact hole is decreased to avoid the formation of the node contact hole from misalignment. However, the contact area between the contact pad and the subsequently formed node contact is decreased due to the decreasing of the size of the node contact hole, so that contact resistance is increased.